1. Field of the Invention
The present invention relates in general to a delay circuit employing switching transistors to delay a signal, and in particular to a delay circuit that adjustably allocates load current between switching transistors of differing speed to adjust an amount by which it delays the signal.
2. Description of Related Art
A signal may be delayed by a precisely adjustable amount, for example by passing it though a series of buffers. Since each buffer has an inherent delay, we can adjust the signal delay by adjusting the number of buffers in the signal's path. However while the resolution such a delay circuit provides is limited to the unit delay of one buffer, we often want to be able to adjust a signal delay with a resolution much smaller than the inherent delay of one buffer.
A delay circuit formed by a single differential amplifier has been employed to delay a signal with a delay that can be finely adjusted. A conventional differential amplifier can be formed by a pair of bipolar transistors. An input signal to be delayed is applied across the transistor bases. The collectors of the two transistors are connected to a voltage source though separate load resistors and the amplifier's output signal appears across the two collectors. The emitters of the differential transistor pair are tied to a common current source that draws a load current through the collector-emitter path of the transistor that is turned on. The state of the input signal determines which transistor is turned on and which transistor is turned off. The output signal state depends on which transistor conducts the current from the current source. The delay between state changes in the input and output signals is a function of the switching speed of the transistors, and the switching speed of the transistors is in turn a function of the load current through the transistors. It is known to adjust the delay of the amplifier by adjusting the magnitude of the load current drawn by the current source.
One drawback to using such an amplifier as an adjustable delay circuit is that the output signal voltage is also a function of the load current; when we change that load current to alter the circuit delay, we change the output signal voltage. That is an undesirable effect.
U.S. Pat. No. 4,866,314 issued Sep. 12, 1989 to Einar O. Traa describes an adjustable delay circuit which uses a differential amplifier to delay a signal but which also maintains its output signal voltage at a constant level over its full delay range. The differential amplifier employs two emitter-coupled transistor pairs instead of one. Transistors of one of the pairs have larger junctions and slower switching speeds than transistors of the other pair. The bases of both transistor pairs are driven by the input signal to be delayed, and the collectors of transistors of both pairs are linked to a voltage source through the same pair of load resistors so that the output signal appears across the collectors of both transistor pairs. However a control circuit adjustably allocates a constant load current drawn by a current source between emitters of the two transistor pairs in response to an input control signal. When the control circuit allocates all of the load current through the slower transistor pair, the delay between state changes in the input and output signals is at a maximum because only the slower transistor pair is active. When the control circuit directs all of the load current through the faster transistor pair, the signal path delay is at a minimum because only the faster transistor pair is active. When the control circuit allocates portions of the load current to both transistors pairs, the signal path delay falls somewhere between its minimum and maximum values depending on the relative amount of load current allocated to each transistor pair. Since the same total amount of load current passes through the load resistors regardless of how much of that load current each transistor pair conducts, the output signal voltage remains constant despite the amount of current allocated to each transistor pair
One disadvantage to this delay circuit is that it provides a relatively limited range of delays. The delay circuit is particularly limited in its ability to provide very short delays. Since the relatively large parasitic capacitances at the bases of the large, slow transistors appear in parallel with the relatively small parasitic capacitances at the bases of the fast transistors, the input signal has to charge both capacitances in order to switch the small transistors even when the large transistors are not conducting any load current. Thus the minimum delay of the circuit is substantially longer than the switching delay of the fast transistor pair would be had the input signal not had to charge the capacitance at the bases of the slow transistor pair.
What is needed is a programmable delay circuit for delaying in input signal with an adjustable delay to produce an output signal having a constant voltage regardless of the delay. The delay provided by the delay circuit should desirably range between a minimum delay near the switching speed of a very fast transistor and a maximum delay near the switching speed of a relatively slow transistor.